Daniel A. Reed is Microsoft’s Scalable and Multicore Computing Strategist, responsible for re-envisioning the data center of the future. Previously, he was the Chancellor’s Eminent Professor at UNC Chapel Hill, as well as the Director of the Renaissance Computing Institute (RENCI) and the Chancellor’s Senior Advisor for Strategy and Innovation for UNC Chapel Hill. Dr. Reed has served as a member of the U.S. President’s Council of Advisors on Science and Technology (PCAST) and as a member of the President’s Information Technology Advisory Committee (PITAC). He recently chaired a review of the U.S. networking and IT research portfolio, and he recently completed a term as chair of the board of directors of the Computing Research Association.

He was previously Head of the Department of Computer Science at the University of Illinois at Urbana-Champaign (UIUC). He has also been Director of the National Center for Supercomputing Applications (NCSA) at UIUC, where he also led National Computational Science Alliance. He was also one of the principal investigators and chief architect for the NSF TeraGrid. He received his PhD in computer science in 1983 from Purdue University.

Most modern processors are in denial about two critical aspects of machine organization: parallel execution and hierarchical memory organization. These processors present an illusion of sequential execution and uniform, flat memory. The evolution of these sequential, latency-optimized processors is at an end, and their performance is increasing only slowly over time. In contrast, the performance of throughput-optimized processors, like GPUs, continues to scale at historical rates. Throughput processors embrace, rather than deny, parallelism and memory hierarchy to realize their performance and efficiency advantage compared to conventional processors. Throughput processors have hundreds of cores today and will have thousands of cores by 2015. They will deliver most of the performance, and most of the user value, in future computer systems.

This talk will discuss some of the challenges and opportunities in the architecture and programming of future throughput processors. In these processors, performance derives from parallelism and efficiency derives from locality. Parallelism can take advantage of the plentiful and inexpensive arithmetic units in a throughput processor. Without locality, however, bandwidth quickly becomes a bottleneck. Communication bandwidth, not arithmetic is the critical resource in a modern computing system that dominates cost, performance, and power. This talk will discuss exploitation of parallelism and locality with examples drawn from the Imagine and Merrimac projects, from NVIDIA GPUs, and from three generations of stream programming systems.

After the explosive growth of the Internet, the computer industry is poised for a second transformation, in which supercomputing technology is headed to corporate data centers and desktop PCs, supplying them with unprecedented compute power. The technology that was once used by government research labs, top universities and a few huge corporations will soon be used to transform everyday computing. So what’s holding us back from connecting advances in graphics processing like physics and the spread of high-speed internet connections to create more immersive online worlds with realistic graphics and personalized information spaces? “What if logging onto the Web meant joining a global-scale physical simulation already in progress?”

In his keynote Intel Corporate Chief Technology Officer Justin Rattner will talk about how we can usher in this new revolution by deftly combining the energy efficiency and performance gains in hardware with advances in software and programming techniques. He will talk about Intel’s research programs that are striving to bring this massive scale of computing to the masses. He will address hardware challenges with scaling multi-core architectures to integrate programmable cores and fixed-function accelerators, flexible cache and memory hierarchy, and high bandwidth on-die networks to ensure high throughput and much more. The talk will then complement hardware with research on parallel programming tools, thread-aware execution environments and showcase future applications like integrated real-time physics and visualization and non-textual media mining. And finally he will share the challenges of moving to Exa-Scale machines by 2018.