HiPC 2016 Accepted Papers - By Technical Session

Preliminary Technical Program

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December 19, 2016 - Day 1

  • HiPC 2016 Workshops

December 20, 2016 - Day 2


Genomes Galore: Big Data Challenges in the Life Sciences
Srinivas Aluru, Georgia Institute of Technology, USA

Technical Session 1: Applications

  • Which Verification for Soft Error Detection?
    Leonardo Bautista-Gomez (Argonne National Laboratory, USA); Anne Benoit and Aurelien Cavelan (ENS Lyon, France); Saurabh Kumar Raina (Jaypee Institute of Information Technology, India); Yves Robert and Hongyang Sun (ENS Lyon, France)

  • Throughput Regulation in Shared Memory Multicore Processors
    Sudhakar Yalamanchili, Xinwei Chen, He Xiao and Yorai Wardi (Georgia Institute of Technology, USA)

  • Application Taxonomy via Algorithmic Commonality for Domain-specific Architecture Design
    Yuanrong Wang and Qiangqiang Li (University of Chinese Academy of Sciences, P.R. China); Guangming Tan (Institute of Computing Technology, Chinese Academy of Sciences, P.R. China)

  • FlexCore: A Reconfigurable Processor Supporting Flexible, Dynamic Morphing
    Furat Afram and Kanad Ghose (State University of New York at Binghamton, USA)

  • High Efficiency Generalized Parallel Counters for Xilinx FPGAs
    Burhan Khurshid and Roohie Naaz (National Institute of Technology, Srinagar, India)

  • 2QW-Clock: An efficient SSD buffer management algorithm
    Dan He (Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology & School of Information Engineering, Nanchang Hangkong University, Nanchang, P.R. China); Ning Liu and Ying He (Huazhong University of Science and Technology, P.R. China)

  • Technical Session 2: Algorithms for data and data management

  • Task-based multifrontal QR solver for GPU-accelerated multicore architectures
    Emmanuel Agullo (INRIA / LaBRI, France); Alfredo Buttari (CNRS - IRIT Toulouse, France); Abdou Guermouche (Université de Bordeaux, France); Florent Lopez (Université Paul Sabatier, France)

  • Structural Agnostic SpMV: Adapting CSR-Adaptive for Irregular Matrices
    Mayank Daga (Advanced Micro Devices, Inc, USA); Joseph L Greathouse (AMD Research, USA)

  • On the resilience of parallel sparse hybrid solvers
    Emmanuel Agullo (INRIA / LaBRI, France); Luc Giraud (Inria, France); Mawussi Zounon (INRIA, France)

  • New Tridiagonal Systems Solvers on GPU architectures
    Adrián P. Diéguez, Margarita Amor and Ramón Doallo (University of A Coruña, Spain)

  • A Stable Parallel Algorithm for Diagonally Dominant Tridiagonal Linear Systems
    S. Chandra Sekhara Rao and Rabia Kamra (Indian Institute of Technology Delhi, India)

  • Technical Session 3: Memory and I/O

  • Optimizing Approximate Weighted Matching on Nvidia Kepler K40
    Md Naim and Fredrik Manne (University of Bergen, Norway); Mahantesh Halappanavar and Antonino Tumeo (Pacific Northwest National Laboratory, USA); Johannes Langguth (Simula Research Laboratory, Norway)

  • Improving Communication Throughput by Multipath Load Balancing on Blue Gene/Q
    Huy Bui (University of Illinois at Chicago, USA); Preeti Malakar, Venkatram Vishwanath, Todd Munson and Eun-Sung Jung (Argonne National Laboratory, USA); Andrew E Johnson (University of Illinois at Chicago, USA); Michael Papka (Argonne National Laboratory, USA); Jason Leigh (University of Hawaii at Manoa, USA)

  • Dynamic Adaptation for Elastic System Services using Virtual Servers
    Abhishek Kulkarni (Indiana University, USA); Hugh Greenberg and Michael Lang (Los Alamos National Laboratory, USA); Andrew Lumsdaine (Indiana University, USA)

  • Understanding the Benefits of Asynchronous Data Transfers in Media Processors
    Nagendra Gulur and Suriya Narayanan L (Texas Instruments, India)

  • HTM Based Speculative Parallel Discrete Event Simulation of Very Fine Grain Models
    Emanuele Santini (DIAG, Italy); Alessandro Pellegrini and Francesco Quaglia (University of Rome "La Sapienza", Italy)

  • Towards Practical Page Placement for a Green Memory Manager
    Ashish Panwar and Kanchi Gopinath (Indian Institute of Science, India)

  • December 21, 2016 - Day 3


    China’s HPC development in the next 5 years
    Depei Qian, Sun Yat-sen University and Beihang University, China

    Technical Session 4: Numerical applications

  • Efficient Barrier Implementation on the POWER8 Processor
    C. D. Sudheer (IBM IRL, India); Ashok Srinivasan (Florida State University, USA)

  • On Accelerating Concurrent PCA Computations for Financial Risk Applications
    Anubhav Jain (TCS, India); Mayank Bakshi, Amit Kalele and Easwar Subramanian (Tata Consultancy Services, India)

  • A Performance Model for GPU-Accelerated FDTD Applications
    Paul Baumeister and Thorsten Hater (Forschungszentrum Juelich, Germany); Jiri Kraus (NVIDIA, Germany); Dirk Pleiter (Forschungszentrum Jülich & Jülich Supercomputing Centre, Germany); Pierre Wahl (Vrije Universiteit Brussel and Luceda Photonics, Belgium)

  • Vectorized Big Integer Operations for Cryptosystems on Intel MIC Platform
    Cheng Chang and Shun Yao (Stony Brook University, USA); Dantong Yu (BNL, Upton, USA)

  • Characterizing Large Dataset GPU Compute Workloads Targeting Systems with Die-Stacked Memory
    Gautam Hazari (Advanced Micro Devices, Inc. (AMD), India)

  • A GPU-based MIS Aggregation Strategy
    T. Lewis, Shankar Sastry, Mike Kirby and Ross Whitaker (University of Utah, USA)

  • Technical Session 5: Resilience and compilers

  • High Throughput Hierarchical Heavy Hitter Detection in Data Streams
    Da Tong and Viktor K. Prasanna (University of Southern California, USA)

  • Offloaded GPU Collectives using CORE-Direct and CUDA Capabilities on IB Clusters
    Akshay Venkatesh, Khaled Hamidouche, Hari Subramoni and Dhabaleswar Panda (The Ohio State University, USA)

  • High Performance OpenSHMEM Strided Communication Support with InfiniBand UMR
    Mingzhe Li, Khaled Hamidouche, Xiaoyi Lu, Jie Zhang, Jian Lin and Dhabaleswar Panda (The Ohio State University, USA)

  • On the Use of Commodity Ethernet Technology in Exascale HPC Systems
    Mariano Benito, Enrique Vallejo and Ramon Beivide (University of Cantabria, Spain)

  • Trigeneous Platforms for Energy Efficient Computing of HPC Applications
    Santhosh Rethinagiri (BSC-Microsoft Research Centre & Barcelona Supercomputing Center, Spain); Oscar Palomar, Francisco Javier Arias Moreno, Adrian Cristal and Osman Unsal (Barcelona Supercomputing Center, Spain)

  • ColdBus: A Near-Optimal Power Efficient Optical Bus
    Eldhose Peter, Arun Thomas, Anuj Dhawan and Smruti Sarangi (IIT Delhi, India) (Indian Institute of Technology Delhi, India)

  • December 22, 2016 - Day 4


    Toward Extreme-Scale Processor Chips
    Josep Torrellas, University of Illinois Urbana-Champaign, USA

    Technical Session 6: Parallel algorithms: Data structures, resource allocation, and linear algebra

  • A Simple BSP-based Model to Predict Execution Time in GPU Applications
    Marcos Amarís, Alfredo Goldman and Daniel Cordeiro (University of São Paulo, Brazil); Raphael de Camargo (Universidade Federal do ABC, Brazil)

  • Partition with side effects
    Fanny Pascual (Universite Pierre et Marie Curie, Poland); Krzysztof Rzadca (University of Warsaw, Poland)

  • Geographically Distributed Load Balancing with (Almost) Arbitrary Load Functions
    Piotr Skowron and Krzysztof Rzadca (University of Warsaw, Poland)

  • Memory-Efficient Parallelization of 3D Lattice Boltzmann Flow Solver on a GPU
    Nhat-Phuong Tran and Myungho Lee (MyongJi University, Korea)

  • Accelerating Complex Event Processing through GPUs
    Prabodha Srimal Rodrigo and Herath Mudiyanselage Nelanga Dilum Bandara (University of Moratuwa, Sri Lanka); Srinath Perera (WSO2 Inc. & University of Moratuwa, Sri Lanka)

  • Technical Session 7: Software architecture

  • Efficient Batched Predecessor Search in Shared Memory on GPUs
    Benjamin Karsin and Henri Casanova (University of Hawaii at Manoa, USA); Nodari Sitchinava (University of Hawaii, USA)

  • Strategies of SIMD computing for image coding in GPU
    Pablo Enfedaque and Francesc Auli-Llinas (Universitat Autonoma de Barcelona, Spain); Juan Carlos Moure (Universidad Autónoma de Barcelona, Spain)

  • IC-Data: Improving Compressed Data Processing in Hadoop
    Adnan Haider, Xi Yang and Ning Liu (Illinois Institute of Technology, USA); Shuibing He (Computer School of Wuhan University, P.R. China); Xian-He Sun (Illinois Institute of Technology, USA)

  • Dominoes: Speculative Repair in Erasure Coded Hadoop System
    Xi Yang (Illinois Institute of Technology, USA); Chen Feng (Institute of Computing Technology, P.R. China); Zhiwei Xu (Institute of Computing Technology, Chinese Academy of Sciences, P.R. China); Xian-He Sun (Illinois Institute of Technology, USA)

  • Collective Offload for Heterogeneous Clusters
    Vicenç Beltran, Jesús Labarta and Florentino Sainz (Barcelona Supercomputing Center, Spain)

  • Meta-scheduling of HPC Jobs in Day-Ahead Electricity Markets
    Prakash Murali and Sathish Vadhiyar (Indian Institute of Science, India)