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TUTORIAL IV
Itanium Architecture and Compiler Optimizations
K. Muthukumar
Intel Technology India Pvt. Limited

Audience: This tutorial is intended for computer professionals, compiler engineers, software developers, researchers, educators, and graduate students interested in learning about the Itanium(TM) architecture and state-of-the-art compiler technologies.

Course Description: Itanium(TM) is Intel's new 64-bit architecture. It is based on the EPIC (Explicitly Parallel Instruction Computing) concept which exploits the high level of Instruction Level Parallelism (ILP) found in application software. To accomplish this goal, Itanium provides a powerful set of features such as control and data speculation, predication, register rotation, loop branches, and a large register file. By using these features, the compiler plays a crucial role in achieving the overall performance of an Itanium platform. This tutorial describes the main features of the Itanium architecture and explains how the various optimization phases in the Intel production compiler for Itanium exploits these features. This will cover: (1) optimizations in the code generator such as predication, global code scheduling, software pipelining, and global register allocation, and (2) other optimizations such as loop unrolling, procedure inlining, inter-procedural analysis, loop-carried scalar replacement, array prefetches, and partial redundancy elimination. This tutorial will help the participant appreciate the many novel features of Itanium, the opportunities they provide for exploiting ILP in application code, and how these have been exploited in a production compiler.

Lecturer: Dr. K. Muthukumar is an Engineering Manager at Intel India Technology Private Limited, Bangalore and a technical lead of the Itanium Compiler group in Santa Clara, California. He heads the Bangalore Compiler Lab at Intel. He has implemented several optimizations in the software-pipelining phase of the compiler. His interests are in compiler optimization, and computer architecture. Prior to joining Intel, he worked at IBM and Apple Computer. He obtained his B. Tech from IIT, Madras, M. S. from the Rensselaer Polytechnic Institute, and Ph. D. in Computer Science from the University of Texas at Austin. He has published many papers in the area of compiler optimization. He has submitted 6 patent applications related to his work on Itanium compiler technology.