HiPC - International Conference on High Performance Computing
       
 
       
   
 
 
 
  18th December 2007
  Tutorial I [8:00 am - 12:00 pm]
  Sensor Networks
  Presenter: Prof. Dharma P. Agrawal, OBR Distinguished Professor of Computer Science, University of Cincinnati, USA
   
  Abstract
  The objective of this tutorial is to fully understand issues in designing Sensor Networks. The impact of coverage area of each sensor will be presented and communications requirements will be established. The energy consumed by a sensor unit will be quantified and different ways of optimizing energy consumption will be explained. Several possible applications of sensor networks in many civilian areas will be explored and ways of collecting sensed data will be examined. Protocols used for medium access, link layer and routing layer will be considered. Both flat and hierarchical topologies will be explored. The attendees will not only understand and position themselves in this hot area of sensor networks, but will also able to develop new capabilities, enhance skills and share their knowledge.
 
  Tutorial II [2.00 pm - 6.00 pm]
  Programming Models and Compiler Optimizations for GPUs and Multi-core Processors
  Presenters: Prof. J. Ramanujam, Professor, Department of Electrical and Computer Engineering, Louisiana State University, USA
Prof. P. Sadayappan, Professor, Department of Computer Science and Engineering, The Ohio State University, USA
   
  Abstract
  Commodity computing components are exhibiting increasing degrees of on-chip parallelism, making parallel execution a characteristic of mainstream computing. A single GPU (Graphics Processing Unit) now has a peak performance of around 0.5 Teraflops for general-purpose computing, using 128 floating-point units on a single chip. As commodity computing platforms all go parallel, an important issue is that of programming them to attain high performance. There has been considerable recent interest both in developing programming models that explicitly expose the programmer to parallelism, as well as compiler optimization frameworks to automatically transform sequential programs for parallel execution. This tutorial will provide an introductory survey covering both these aspects.
  Additional information about the tutorials will be posted soon.
 
  Tutorials Chair
  Rajeev Sivaram, Google, USA
 
   
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