Workshop on Memory and Storage Systems 2019 (WoMSS 2019)

HiPC 2019

The bottlenecks in contemporary high performance computer systems are shifting from compute to memory and storage subsystems. Applications in the HPC and hyperscale domains have seen a tremendous growth in the amount of data they are required to process, many times under very strict service level agreements (SLAs).  This has exacerbated the need for high bandwidth, low latency, and high capacity memory system design, possibly using a number of emerging memory technologies including, but not limited to PCM, STT-RAM, and Memristors.

The storage subsystem has been experiencing similar trends. Current industry trends forecast the incorporation of emerging memory technologies like 3D-XPoint and PCM into high performance storage devices in the very near future. As a result of these developments, the future memory and storage hierarchies will comprise of a number of varied memory technologies. In order to get ahead of these emerging trends, there is an immediate need to revisit various areas of memory and storage system design, as well as the system software stack to address these challenges. Also, with the emergence of timing attacks, side-channel and covert channel attacks are getting disclosed frequently. The workshop also welcomes preliminary and mature ideas in the sub-field of memory system security.

The goal of this workshop is to bring together academic researchers and industry practitioners to share their insights from different perspectives (memory and storage systems design, including but not limited to system software, firmware, and architecture) and discuss the problems pertaining to the design of memory and storage systems of tomorrow’s high performance machines.


Topics to be addressed, but are not limited to

  • Main memory architecture
  • Emerging memory technologies
  • Storage class memory
  • Innovative cache architectures for contemporary and emerging workloads
  • System interfaces design for memory and storage architectures
  • Operating system optimizations for memory and storage systems
  • High-speed storage architecture and design
  • Performance, power, and energy modeling and analysis of memory and storage systems
  • Co-design of memory and storage systems
  • Design of remote memory and storage hierarchies
  • Application level optimizations for memory and storage
  • Processing in/near memory (PIM/PNM)
  • Memory system security, Timing Channels, ORAMs, Fault attacks
  • Reliability issues in memory and storage
  • Memory design issues in deep neural networks and machine learning


Manuscript Guidelines

Submitted manuscripts should be structured as technical papers and may not exceed six (6) single-spaced double-column pages using 10-point size font on 8.5 × 11 inch pages (IEEE conference style), including figures, tables, and references. See IEEE style templates at this page for details.

Electronic submissions must be in the form of a readable PDF file. All manuscripts will be reviewed by the Program Committee and evaluated on originality, relevance of the problem to the conference theme, technical strength, rigor in analysis, quality of results, and organization and clarity of presentation of the paper.

Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal. Papers not following these guidelines will be rejected without review and further action may be taken, including (but not limited to) notifications sent to the heads of the institutions of the authors and sponsors of the conference.

Presentation of an accepted paper at the workshop is a requirement of publication. Any paper that is not presented at the conference will not be included in the proceedings.

Submission Portal:


Important Dates

Paper Submission: September 20, 2019

Author Notification: October 20, 2019

Camera Ready Submission: October 28, 2019


Program Committee

Prof. Mainak Chaudhuri (IIT Kanpur)

Prof. Debadatta Mishra (IIT Kanpur)

Dr. Niladrish Chatterjee (Nvidia Research)

Prof. Sparsh Mittal (IIT Hyderabad)

Prof. Arkaprava Basu (IISc Bangalore)

Prof. Adwait Jog (College of William and Mary)



Organising Committee

Prof. Manu Awasthi (Ashoka University)

Prof. Biswabandan Panda (IIT Kanpur)


Contact Details:

Manu Awasthi, Ashoka University




Biswabadan Panda, IIT Kanpur




Chandan Kumar Jha, IIT Gandhinagar

Web/Submission Chair

















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