High Performance Computing has been a critical tool in understanding predicting climate change, and exascale computing combined with advances in mathematical modeling and parallel algorithm will lead to new insights in climate impacts, including the prevalence of hurricanes, droughts, wildfires and more. But the role for HPC in climate science goes well beyond physical modeling to the development of mitigation and adaptation strategies, and the use of high performance data analytics based with both traditional algorithms and machine learning. An explosion of new data sources from satellite imagery and embedded environmental sensors to portable genome sequencers and personal mobile phone data will transform our ability to monitor, infer and manage responses to a changing climate. What is the role of machine learning and HPC in climate change and how do the data-intensive problems change the requirements on hardware, programming support, parallel algorithms, and architecture? I will give an overview of several high performance modeling and analysis problems, their potential impacts on climate change and opportunities for mapping these to exascale architectures.
Katherine Yelick is the Robert S. Pepper Distinguished Professor of Electrical Engineering and Computer Sciences and the Associate Dean for Research in the Division of Computing, Data Science and Society (CDSS) at the University of California, Berkeley. She is also a Senior Advisor on Computing at Lawrence Berkeley National Laboratory. Her research is in high performance computing, programming systems, parallel algorithms, and computational genomics and she currently leads the ExaBiome project on Exascale Solutions for Microbiome Analysis.
Yelick was Director of the National Energy Research Scientific Computing Center (NERSC) from 2008 to 2012 and the led the Computing Sciences Area at Berkeley Lab from 2010 through 2019, where she oversaw NERSC, the Energy Sciences Network (ESnet) and the Computational Research Division. She earned her Ph.D. in Electrical Engineering and Computer Science from MIT and has been a professor at UC Berkeley since 1991 with a joint research appointment at Berkeley Lab since 1996. Yelick is a member of the National Academy of Engineering and the American Academy of Arts and Sciences. She is a Fellow of the Association for Computing Machinery (ACM) and the American Association for the Advancement of Sciences (AAAS). She is a recipient of the ACM/IEEE Ken Kennedy award and the ACM-W Athena award.
Scale has been central to the success of deep learning with the availability of large-scale data and compute infrastructure. However, for further progress, scale has to be coupled with novel algorithms. Next-generation AI will be unsupervised, robust and adaptive. It will incorporate more structure and domain knowledge. Examples include tensors, graphs, physical laws, and simulations. I will describe efficient frameworks that enable developers to easily prototype such models, e.g. Tensorly to incorporate tensorized architectures, NVIDIA Isaac to incorporate physically valid simulations and NVIDIA RAPIDS for end-to-end data analytics. I will then lay out some outstanding problems in this area.
Anima Anandkumar is a Bren Professor at Caltech and Director of ML Research at NVIDIA. She was previously a Principal Scientist at Amazon Web Services. She has received several honors such as Alfred. P. Sloan Fellowship, NSF Career Award, Young investigator awards from DoD, and Faculty Fellowships from Microsoft, Google, Facebook, and Adobe. She is part of the World Economic Forum’s Expert Network. She is passionate about designing principled AI algorithms and applying them in interdisciplinary applications. Her research focus is on unsupervised AI, optimization, and tensor methods.
While HPC systems have considerably improved their raw compute performance and scalability over the last two decades – first with the adoption of compute clusters and then throughput computing – good communication performance and overall scalability are still very difficult to achieve with irregular and communication intensive sparse linear algebra and graph applications. Recent advances in chip packaging, such as Embedded Multi-die Interconnect Bridge (EMIB), novel Optical IO Photonics modules that can be directly integrated on chip, and aggressive system designs that eliminate the SW stack and natively support a Distributed Global Address Space, can be used to improve overall performance and potentially break the scalability wall of state of the arts computing systems.
Fabrizio Petrini is a Principal Engineer of the Intel Parallel Computing Labs in Santa Clara, CA. His research interests include data-intensive algorithms, high performance interconnection networks and novel architectures for graph analytics and sparse linear algebra. He is the Co-Principal investigator of the Intel DARPA HIVE and SDH programs that will deliver the first version of the Programmable Integrated Unified Memory Architecture (PIUMA) in late 2021. Fabrizio has published over 120 peer-reviewed journal and conference articles which received 6000 citations and is serving as associate editor for the IEEE Transactions on Computers. He received a PhD in Computer Science from the University of Pisa, Italy, and was a postdoc at UC Berkeley and a research fellow at the Computing Laboratory of the Oxford University in the UK.