1^st ROCS Workshop: RecOnfigurable Computing and Systems Workshop 2024

Dec 18, 2024
Bengaluru, India

In conjunction with the 31st IEEE International Conference on High-Performance Computing, Data, & Analytics (HiPC 2024)

Description:

Reconfigurable computing involves using hardware that can be dynamically reprogrammed to optimize performance for specific tasks. Heterogeneous computing combines different types of compute elements to handle diverse workloads efficiently. Field-Programmable Gate Arrays (FPGAs) are mainly used for reconfigurable computing, and are crucial for high-performance computing applications and accelerating machine learning (ML) applications. Unlike general-purpose CPUs and GPUs, FPGAs can be reconfigured to execute repetitive and computationally intense operations, offering better energy efficiency. The Reconfigurable Computing and Systems Workshop (ROCS) is the first edition running in conjunction with HIPC, aimed at attracting participants to discuss aspects of reconfigurable and heterogeneous computing systems. The broad topics of interest include architecture, programming methodologies, heterogeneous computing, applications such as ML acceleration, embedded systems, IoT devices, telecommunications, data center accelerators and related areas.

Schedule:

Keynote:

Vijayavardhan Baireddy

Director (Product), Morphing Machines

Bio: Vijay has had over 20+ years of experience in Semiconductor Industry. He worked with Texas Instruments, Xilinx (now AMD) and Intel where he led the designs of high-performance and low-power solutions for various domains including machine learning, computer vision and signal processing. Vijay did his BTech (Hons) in Electrical Engineering from IIT Kharagpur and MTech in Electronics Design and technology from Indian Institute of Science (IISc) Bangalore.

Title: Reconfigurable High-Performance Computing: Challenges, Opportunities and the Road Ahead

Abstract: Relevance of RC (Reconfigurable Computing) in HPC (High-Performance Computing). RC is generally associated with FPGAs and Coarse-Grained Reconfigurable Array (CGRA)’s. There is also a processor-like RC. There are many opportunities & challenges with new RC techniques. The road ahead will be explored in this presentation.

Fireside talk: Career talk

Dr. Natesan Venkateswaran

Program Director, EDA Analysis; AI Ethics Champion; Master Inventor;

Bio: Natesan is the Program Director for Analysis at IBM Electronic Design Automation (EDA), delivering the tools and methodology needed for the design, verification, and sign off of IBM Power and Z microprocessors. In his 28-year career at IBM, Natesan has held several technical leadership, and management roles in EDA. He presently leads a global team of engineers in developing innovative solutions for gate level and transistor level Timing, Noise, and Power analysis. Furthermore, Natesan’s team develops tools used in circuit simulation and library characterization. Natesan has 59 patents till date, an IBM Master Inventor, and serves at the IBM Council for Innovation Leadership. He is also a leader of the IBM Open Innovation Community – a community which focuses on promoting technical vitality within and outside of IBM.

Prof. Viktor K. Prasanna

Professor of Electrical and Computer Engineering and Professor of Computer Science

University of Southern California

Bio: Viktor K. Prasanna (V. K. Prasanna Kumar) is Charles Lee Powell Chair in Engineering and is Professor of Electrical Engineering and Professor of Computer Science at the University of Southern California (USC) and serves as the director of the Center for Energy Informatics (CEI). His research interests include Parallel and Distributed Computing, Reconfigurable Computing, Accelerator Design and Systems for and applications of ML. Prasanna received the W. Wallace McDowell Award from the IEEE Computer Society in 2015 for his contributions to reconfigurable computing.  He received an Outstanding Engineering Alumnus Award from the Pennsylvania State University in 2009, the Distinguished Alumnus Award from the University Visveswaraya College of Engineering (UVCE) of Bangalore University in 2017 and a 2019 Distinguished Alumnus Award from the Indian Institute of Science (IISc).

Invited talks 

Kamesh Chandrasekar

Fellow, Software Development, Adaptive and Embedded Computing Group, AMD

Title:  Reconfigurable Computing with Design For eXchange (DFX) in Adaptive SoCs

Abstract: In this talk, we will start with a few real-world applications for Adaptive SoCs. We will introduce the Versal Adaptive Compute platform and its evolution from FPGAs. We will discuss the Dynamic Function eXchange (DFX) solution and its benefits that will enable customers to use Adaptive SoCs very effectively. Finally, we will conclude with a few futuristic thoughts on Edge AI as a growth opportunity for Adaptive SoCs.

Bio: Dr. Kameshwar Chandrasekar has worked for 23 years in Electronic Design Automation (EDA) software tools and methodology development. Dr. Chandrasekar received his Masters and PhD in Computer Engineering from Virginia Tech. He started his career in Intel, Santa Clara and worked on customized Automatic Test Pattern Generation (ATPG) solutions for partial scan microprocessor designs. Then, he moved to Xilinx (now AMD), Hyderabad to work on Vivado software development for FPGA designs. He architected and developed the Incremental Synthesis solution for FPGA designs from concept to production in Vivado. He is currently leading a group that works on Design For eXchange (DFX) software tools in Vivado.  He has published 19 research papers in leading international conferences and holds six patents. His areas of interest include: FPGA design tools and software development, Reconfigurable Computing, machine learning, algorithms and EDA solutions.

Ananth Pallapothu

Principal Member of Technical Staff, Chief Engineer of MI Instinct,  Data Center Graphics Organization, AMD

Title of the talk: AMD Instinct™ MI300 Architecture Briefing

Abstract: MI300 is the culmination of years of AMD developments in advanced packaging technologies, its APU hardware and software, and the chiplet strategy to deliver a groundbreaking design for exascale computing and meet the demands of new large language model & generative AI applications. This presentation is intended to provide an architectural view of the compute’s operation, software distribution on the hardware & how Instinct architecture helps attain performance.

Bio: Ananth is currently operating as a Chief Engineer for MI Instinct products. Ananth Lead Enterprise Prototyping (FPGA) technology and Emulation Hardware enablement & user deployment across AMD. Prior to that he has Architected and Developed several Hybrid (Virtual + Hardware) SoC & System solutions for Pre-Silicon (& Emulation) Validation collaborating with across Industry technologists alongside AMD experts, and deployed them across user community. Prior moving to AMD 15 years ago Ananth worked at Oracle, Sonics Inc & IBM in Pre-Silicon & Emulation developing Methodologies, Solutions and Design Verification. Ananth holds Master’s in Electrical Engineering from University of Hartford. His areas of interest include ML/AI algorithms and their distribution into Hardware (computes), System Data Center complexities, Hardware Emulation, Virtual/Hybrid System Solutions, FPGAs.

Prof. Sumit Kumar Mandal

Assistant Professor, Department of Computer Science and Automation (CSA), IISc, Bangalore

Title of the talk: Communication-aware Heterogeneous 2.5D System for Energy-efficient LLM Execution at Edge

Abstract: Large Language Models (LLMs) are used to perform various tasks, especially in the domain of natural language processing (NLP). State-of-the-art LLMs consist of a large number of parameters that necessitate a high volume of computations. Currently, GPUs are the preferred choice of hardware platform to execute LLM inference. However, monolithic GPU-based systems executing large LLMs pose significant drawbacks in terms of fabrication cost and energy efficiency. In this work, we propose a heterogeneous 2.5D chiplet-based architecture for accelerating LLM inference. Thorough experimental evaluations with a wide variety of LLMs show that the proposed 2.5D system provides up to 972 improvement in latency and 1600 improvement in energy consumption with respect to state-of-the-art edge devices equipped with GPU.

Bio: Sumit K. Mandal is currently an assistant professor in Indian Institute of Science, Bangalore. He completed his PhD from University of Wisconsin-Madison. He received best paper award from ACM TODAES in 2020 and ESweek in 2022. His research interest is energy efficient communication architecture for machine learning applications with emerging technologies.

Panel discussion members:

Prof. R. Govindarajan,

Professor, Department of Computer Science and Automation and. Supercomputer Education and Research Center, IISc, Bangalore

Bio: R. Govindarajan received his B.Sc. degree in Mathematics from Madras University in 1981 and B.E. (Electronics and Communication) and Ph.D. (Computer Science) degrees from the Indian Institute of  Science, Bangalore in 1984 and 1989 respectively. He has held postdoctoral research positions and visiting faculty positions at Universities in the USA and Canada.  Since 1995, he has been with the Supercomputer Education and Research Centre and the Department of Computer Science and Automation, Indian Institute of Science, Bangalore.  His research interests are in the areas of High Performance Computing, Compilation Techniques, and Computer Architecture. He has more than 140 research publications in international journals and refereed conferences.  He is a fellow of the Indian National Academy of Engineering, a Senior Member of  the IEEE and a Distinguished Member of the ACC.

Dr. Madhura Purnaprajna

Affiliation: AMD and PES, University

Bio: Madhura is at the Silicon Architecture group at AMD (Xilinx), that looks at performance projection of next-generation adaptive compute devices. She also holds a professor position at PES University (currently on Sabbatical), where her research group works on accelerating applications using heterogeneous compute such as CPU, GPU and FPGAs. Her research interests are in Reconfigurable Computing and opensource EDA.

Prof. Sharad Sinha

Associate Professor, Computer Science and Engineering, Indian Institute of Technology Goa (IIT Goa)

Bio: Dr. Sharad Sinha is an Associate Professor of Computer Science and Engineering at IIT Goa. He is also the Dean of Faculty Affairs, the Head of International Relations and a Member of the Board of Governors of IIT Goa. He received his PhD in Computer Science and Engineering from Nanyang Technological University (NTU), Singapore. 

His research interests are in computer architecture, high performance computing, reconfigurable computing, hardware security and computing systems design for AI and applications of computing in various application areas. He has received Best Paper Awards at ACM/IEEE International Conference in Computer Aided Design (ICCAD) in 2017 and 2022, INDICON 2022. He has also been nominated for Best Paper Awards at IEEE FCCM 2019 and IEEE CASES 2018. He is a recipient of a Special Mention Award during National Voters’ Day 2022 for AI based webcasting and VoterDost chatbot during the Goa State Assembly Elections 2022. He is also the Head of the National Supercomputing Mission Nodal Center for Training in HPC and AI, and the Center for Drone Applications at IIT Goa.

Vivek Yadav

Technology Officer and Adjunct Faculty, IIIT Bangalore

Bio: Vivek Yadav is the Technology Officer at IIIT-Bangalore, where he leads initiatives in enterprise application design and development. He also serves as an Adjunct Faculty, teaching Big Data, software development, and algorithms, and has mentored multiple ACM-ICPC teams to global success. Vivek is the Secretariat Head of the Vision Group under the Directorate of Collegiate Education, Karnataka, driving the implementation of the National Education Policy in the state. Vivek contributes towards advancements in low-code platforms, and Gen-AI through the RASP (rasp.iiitb.net) and MINRO (minro.org) projects. He was a co-founder of FullStackNet, focusing on enterprise mobile applications.  An accomplished academic and innovator, Vivek holds an MS by Research in Information Technology from IIIT-Bangalore. A recipient of multiple accolades, including the Distinguished Alumnus Award from RGPV university, MP and selected for the Stanford Ignite Program, Vivek combines academic rigor, entrepreneurial spirit, and technical expertise to create solutions that bridge research and real-world applications.

Organization committee:

1. Workshop chairs:
   Nanditha Rao, IBM ([email protected])
   Jason Lin, University of Southern California ([email protected])
2. Publicity:
   Nanditha Rao, IBM ([email protected])

• Technical Program Committee:

• Aman Arora – Arizona State University
• Binod Kumar – IIT Jodhpur
• Hemangee Kapoor – IIT Guwahati
• Madhura Purnaprajna – AMD
• Masahiro Fujita- University of Tokyo 
• Nitya Hariharan- Intel
• Sachin Patkar, IIT Bombay
• Sharad Sinha- IIT Goa
• Vipin K- BITS Pilani Goa campus
• Vivek Chaturvedi- IIT Palakkad

Contact: Questions may be sent to [email protected]