HiPC Programming Contest

28th IEEE INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING, DATA, & ANALYTICS

The objective of the HiPC Programming Contest is to introduce bright and motivated students to industry-relevant problems in the area of high performance computing. This engagement will act as a bridge between industry and academia to forge active engagement between the two.
Participation in the programming challenge is free and does not incur any registration fees. The top three teams in each track will be presented with prizes and invited to the virtual HiPC 2021 conference, where they will have the opportunity to present their approach and solutions. After the final notification, each member of the team selected for the presentation must register for the conference, and HiPC provides limited scholarships to register for the conference.

 

Competition Rules

  • The challenge will be open only to full-time students enrolled in Indian institutions and universities.
  • Each team must consist of 1 to 3 student participants.
  • The contest will be held in three parallel and independent tracks.
    • Track A: Intel Architecture
    • Track B: Nvidia GPU Architecture
    • Track C: Xilinx FPGA Architecture
  • Each team may choose to register for one or more tracks.
  • No person can register for two teams in a single track.
  • The contest will be held over a period of 60 days. Timeline for which is given below.
  • Submission acceptance and evaluation criteria:
    • All submissions must be the team’s own work. Plagiarism will be dealt with utmost seriousness and will have serious consequences. We will follow the IEEE rules that apply to papers including adding authors to IEEE Prohibited Authors List Database. The decisions of track and program chairs in any such case will be final. All submissions will be vetted for plagiarism using the MOSS MIT tool. Submissions which are found to be plagiarized will be rejected.
    • Functional correctness of the result is a must to be considered for further evaluation.
    • Scoring Metrics: Evaluation metrics will be made available along with the challenge problem.

 

Competition Tracks

  • The contest will have the following three parallel and independent problem statements:
    • CPU track will be for x86-based CPUs
    • GPU track will consist of a high-end node with an NVidia GPU
    • FPGA track with AWS F1 instances
  • Student teams can submit to one or two or all tracks.
  • The submissions to each track will be evaluated independently and there will be no cross-track comparison.

 

Organizing Committee

 

CPU Track

  • Nagendra GD, University of North Texas
  • Biswabandan Panda, Indian Institute of Technology Bombay
  • Anuj Pathania, University of Amsterdam
  • Amey Karkare, Indian Institute of Technology Kanpur

 

GPU Track

  • Vishwesh Jatala, Indian Institute of Technology Bhilai
  • Jayvant Anantpur, Siemens, USA
  • Manish Modani, Nvidia

 

FPGA Track

  • Madhura Purnaprajna, PES University, Bangalore
  • Vipin Kizheppatt, BITS Pilani, Goa
  • Nithin George, Intel Corporation
  • Nachiket Kapre, University of Waterloo

 

Submission Process

The challenge is divided into two stages. In the first stage, students may deploy and test their submission locally (on their machine or a cluster provided by their institute). After initial testing, in the second stage, each participating group will be given access to a cluster (see Important Dates below) to deploy and test their solutions in an environment similar to the one that will be used for final evaluations. The submission guidelines for each track will be made available along with the challenge problem.

All submissions will be vetted for plagiarism using the MOSS MIT tool. Submissions that are found to be plagiarized will be rejected. The submission link will be posted.

 

Training Sessions

To introduce more students to parallel programming concepts and to encourage high-quality submissions, the contest will host the following online training sessions for the registered students. The sessions will be aimed towards providing an overview and development of best practices for these systems.

  • CPU Track: Intel Devcloud and development tools. Click here for CPU Track training schedule.
  • GPU Track: NVIDIA GPU introduction, CUDA Programming and optimizations. Click here for GPU Track training schedule.
  • FPGA: Xilinx FPGA architectures on AWS and programming concepts. Click here for FPGA Track training schedule.

 

Prizes

The top three teams in each track will be presented with prizes for individual tracks at the HiPC conference. In addition, they will be invited to the virtual HiPC 2021 conference where they will have the opportunity to present their approach and solutions. HiPC provides limited scholarships to register for the conference.

 

Important Dates

Registration Closes: August 16, 2021

Challenge Problem Release: August 31, 2021

Online training sessions (tentative): September 2nd Week, 2021

Teams are given access to cluster for self-evaluation: October 1, 2021

Final Submission Deadline: October 31, 2021

Final Notifications: November 15, 2021

 

All the deadlines are shown in IST (UTC +05:30).

 

Registration

Please use this link to register.

 

Contact

Please note that from now on, all communications to registered participants will happen only through the google group corresponding to each track. For any other queries, please contact [email protected].