Keynote Speakers
Keynote Talks
Title: Training A Large Language Model from Scratch – What does it take?
Speaker: Pratyush Kumar, Assistant Professor, Computer Science and Engineering, Indian Institute of Technology Madras and Co-Founder Sarvam AI.
Time:
Abstract:
Speaker Bio: Dr. Pratyush Kumar is the Co-founder of Sarvam and a leading voice in India’s AI ecosystem. A two-time founder, he previously built AI4Bharat and OneFourth Labs, both instrumental in advancing open-source AI for Indian languages. AI conferences and journals. Prior to founding Sarvam, Dr. Kumar was a researcher at Microsoft Research and IBM, where he worked on cutting-edge problems in machine learning and natural language processing. He has published over 89 research papers at top-tier conferences and journals, contributing to both academic and applied advances in the field. Dr. Kumar holds degrees from IIT Bombay and ETH Zurich and continues to build AI that reaches every corner of the country.
Title: Utilizing LLMs for Parallel Scientific Code Generation and Translation
Speaker: Valerie E. Taylor, Division Director/ Argonne Distinguished Fellow, Mathematics and Computer Science Division, Argonne National Laboratory, USA
Time: 20th December, 2024, 9 AM to 10 AM IST
Abstract: Large language models (LLMs) have the potential to serve as an assistant to aid scientists with scientific discovery. One important area needed for this assistance is that of parallel, scientific code generation. Existing Large language models, such as GPT-x, Codestral, StarCoder, and Code Llama, etc. are being used to generate parallel, scientific code with some limitations. This talk will discuss some of the limitations and present our framework, called LASSI, to address some of the limitations. LASSI, is an LLM-based Automated Self-correcting pipeline for generating parallel ScIentific codes. Currently, LASSI features a pipeline that automatically generates code, tests for compilation, and checks execution. Future work will focus on code performance and correctness.
Speaker Bio: Valerie Taylor is the Director of the Mathematics and Computer Science Division and a Distinguished Fellow at Argonne National Laboratory. Her research is in high-performance computing, with a focus on performance analysis, modeling and tuning of parallel, scientific applications using AI. Her current work is on energy efficient methods.
Prior to joining Argonne, she was the Senior Associate Dean of Academic Affairs in the College of Engineering and a Regents Professor and the Royce E. Wisenbaker Professor in the Department of Computer Science and Engineering at Texas A&M University. In 2003, she joined Texas A&M University as the Department Head of CSE, where she remained in that position until 2011. Prior to joining Texas A&M, Valerie Taylor was a member of the faculty in the EECS Department at Northwestern University for eleven years. She is also the CEO and President of the Center for Minorities and People with Disabilities in IT (CMD-IT), for which she is a co-founder.
Valerie Taylor is an IEEE Fellow, ACM Fellow, and AAAS Fellow. Valerie E. Taylor earned her B.S. in ECE and M.S. in Computer Engineering from Purdue University in 1985 and 1986, respectively, and a Ph.D. in EECS from the University of California, Berkeley in 1991.
Title: Agile Design of Domain-Specific Hardware Accelerators and Compilers
Speaker: Priyanka Raina, Assistant Professor, Electrical Engineering, Stanford University, USA
Time: 21st December, 2024, 9 AM to 10 AM IST
Abstract: With the slowing of Moore’s law, computer architects have turned to domain-specific hardware accelerators to improve the performance and efficiency of computing systems. However, programming these systems entails significant modifications to the software stack to properly leverage the specialized hardware. Moreover, the accelerators become obsolete quickly as the applications evolve. What is needed is a structured approach for generating programmable accelerators and for updating the software compiler as the accelerator architecture evolves with the applications. In this talk, I will describe a new agile methodology for co-designing programmable hardware accelerators and compilers. Our methodology employs a combination of new programming languages and formal methods to automatically generate the accelerator hardware and its compiler from a single specification. This enables faster evolution and optimization of accelerators, because of the availability of a working compiler. I will showcase this methodology using Amber, a coarse-grained programmable accelerator for imaging and machine learning (ML) we designed and fabricated using our flow in TSMC 16 nm technology. I will show how we agilely evolved Amber into Onyx, our next generation accelerator, using an application-driven design space exploration framework called APEX enabled by our hardware-compiler co-design flow.
Speaker Bio: Priyanka Raina received the B.Tech. degree in Electrical Engineering from IIT Delhi in 2011, and the M.S. and Ph.D. degrees in Electrical Engineering and Computer Science from MIT in 2013 and 2018, respectively. She was a Visiting Research Scientist with NVIDIA Corporation in 2018. Since 2018 she is an Assistant Professor of Electrical Engineering at Stanford University, where she works on domain-specific hardware architectures and agile hardware–software codesign methodology.
Dr. Raina is a 2018 Terman Faculty Fellow. She was a co-recipient of the Best Demo Paper Award at VLSI 2022, the Best Student Paper Award at VLSI 2021, the IEEE Journal of Solid-State Circuits (JSSC) Best Paper Award in 2020, the Best Paper Award at MICRO 2019, and the Best Young Scientist Paper Award at ESSCIRC 2016. She has won the DARPA Young Faculty Award in 2024, Sloan Research Fellowship in 2024, the National Science Foundation (NSF) CAREER Award in 2023, the Intel Rising Star Faculty Award in 2021, and the Hellman Faculty Scholar Award in 2019. She was the Program Chair of the IEEE Hot Chips in 2020. She serves as an Associate Editor for the IEEE Journal of Solid-State Circuits and IEEE Solid-State Circuits Letters.
HiPC 2025 is the 32st edition of the IEEE International Conference on High Performance Computing, Data, and Analytics. It will be an in-person event in Hyderabad, India, from December 17 to December 20, 2025.
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