HiPC 2017 has organized two tutorials that will be conducted as two-hour sessions on Day 1 of the conference (December 18th). Tutorials offer attendees the chance to learn from and to interact with leading experts in popular areas of high performance computing, data, and analytics.
They are being held on Day 1 so that attendees may attend prior to the three days of the technical program and industry exhibits and events. It also offers students an opportunity to participate before they need to be available for the Student Research Symposium held on Days 2 and 3.
The HiPC 2017 tutorials, open to all attendees, will provide a survey of a selected development in a key emerging area of our field. Below are brief descriptions of each tutorial. We will be posting additional information, like target audience and presenter links, so please return to this page in the coming weeks.
Title : Introduction to Power Optimization Techniques in HPC
Soham Ghosh, C-DAC, India
Sharda Dixit, C-DAC, India
Ritu Arora, TACC, USA
Title : Programming FPGAs for HPC applications using OpenCL
Presenters: Nitya Hariharan & Kai-Feng Chou, Intel, Corporation
This is hands-on tutorial and limited seats are available. To attend the tutorial register here.
Field Programmable Gate Arrays (FPGAs) are increasingly popular in providing a flexible solution for meeting customer requirements in different domains. Along with CPUs, they provide a platform that can be rapidly re-designed for a specific problem with a much shorter time-to-market and enhanced performance than CPU only solutions. The tutorial has been designed for software engineers by providing an introduction to FPGAs, their programming with Software Development Toolkits (SDK) (1), high-level synthesis (HLS) (2) and a practical example of optimizing a HPC compute kernel.
Intel provides a host of software tools that let software engineers develop solution on FPGA by using High-level Languages – OpenCL or C/ C++. Now, programming FPGAs is no longer as difficult as it was once considered to be!
The workshop is separated into three parts –
1) High Level design Introduction and market trend analytics
2) Hands-on tutorial and Optimization tips of OpenCL kernels
3) HLS Introduction, use with C/C++ algorithm modules, and short demo
Outcome – Provides a step-by-step introduction to using FPGAs, right from setting up the environment to running the code on the emulator and optimizing the code on the emulator. Finally, the process of setting up and running the code on the FPGA will be demonstrated. This should get people on looking at opportunities for optimizing compute intensive codes on the FPGA.
1. Altera OpenCL SDK, https://www.altera.com/products/design-software/embedded-software-developers/opencl/overview.tablet.html
2. HLS – https://www.altera.com/products/design-software/high-level-design/intel-hls-compiler/overview.html
Basic OpenCL knowledge, understanding of FPGAs, C/C++ knowledge.
Participants can bring their own laptop.
Nitya Hariharan is a Senior Application Engineer at Intel. She has over 10 years of experience in parallel computing and software development. Her interests lie in application optimization on CUPs and accelerators like FPGAs, she finds inter disciplinary projects combining computer science with natural sciences to be fascinating. In her current role she collaborates with users to enable and optimize their codes on the Xeon and Xeon Phi architecture.
Maple Chou joined Intel PSG (Altera) in 2011, since when he started his professional for SoCFPGA design and High-Level Design for FPGA. He is in charge of OpenCL, HLS and SoCFPGA technical support and promotion. Before he joined Intel PSG, he has experience with Compiler of Parallel Programming (GPU), Embedded Software Design and Linux Kernel Driver.