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TUTORIAL IV
The Early 21st-Century Processor Architecture Landscape
Sriram Vajapeyam
Independent Consultant

Audience: Any one interested in a quick but comprehensive overview of the current processor landscape and having (a) basic background in computer architecture and organization, and (b) some exposure to advanced processor architecture. The tutorial should be useful to a variety of people in the field, including decision makers, technical managers, practicing engineers, research students and faculty members.

Course Description: Processors today populate a variety of markets and application domains: the traditional high-end servers, desktop and mobile computers; embedded computers, especially DSPs, network processors, etc. Traditionally, the advanced micro-architectural features used in processors, within the von Neumann model framework, have trickled down from supercomputers to workstations to PCs. While this trend continues today with embedded processors, DSPs, etc., these newer domains also incorporate processor features and technologies specially suited for just their applications. In this tutorial, we will provide a quick overview of this increasingly complex processor architecture landscape. We first identify and classify several basic processor micro-architectural techniques in the contexts of a typical general-purpose super-scalar processor model and a vector processor model. Extensive speculative processing, multi-threading, modular and hierarchically decoupled instruction issue, and dynamic code optimization are some of the more important trends in traditional high-performance CPUs. Next, we will contrast the general-purpose workload's characteristics with those of the DSP and network processing domains. This will serve as a springboard for looking at the processors (micro-architectures) of those domains. For example, vector-style processing is an important feature in DSP processors. Throughout, we will highlight example features from commercial processors of the respective domains. Finally, we will touch upon the exciting less-traditional aspects of the current processor landscape. Dynamic cross-platform binary translation (and code optimization) is breaking the traditional binary compatibility lock in general-purpose and high-end computing. The newer computing domains employ important technologies such as configurable/reusable IP cores, reconfigurable fabrics, system-on-chip, special-purpose co-processors, (automated) processor customization and specialization, etc. We will provide a quick glimpse of several of these technologies. Overall, the tutorial attendee will get a bird's eye view of significant architectural and technological trends in processors for the different computing domains.

Lecturer: Sriram Vajapeyam is currently an independent consultant in computer architecture and systems. He holds a Ph.D. (1991) and an M.S. in Computer Science from the University of Wisconsin-Madison, and a B.Tech. in Electrical Engineering from IIT-Madras. Vajapeyam worked for a year at Cray Research ('91-'92) after his Ph.D., and has done a 6-month sabbatical at Analog Devices India, a 3-month Visiting Professorship at Intel Microprocessor Research Labs, and 8+ years in a faculty position in India. He has held several short-term visiting positions including at MIT, Univ. of Wisconsin, Cray Research, Univ. of Southern California (LA), and ACRI France. He has taught half a dozen tutorials at the top international computer architecture conferences (ISCA and ASPLOS) and written a guest-editorial on processors for IEEE Computer. Vajapeyam's research and professional interests are in computer architecture and systems.