HiPC International Conference On High Performance Computing
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HiPC 2002 - Bangalore, India - December 18-21
Bangalore Palace
Advance Program
Program Highlights
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Poster/Presentation Session
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Advanced Program

Thursday Dec. 19th

8 :3 0 a m - 9 :0 0 a m
INAUGURATION
by
V. Kulakarni, IAS
Department of Information Technology & Biotechnology
Govt. of Karnataka

Guest of Honor
S. Sadagopan
Indian Institute of Information Technology, Bangalore

OPENING REMARKS
Viktor K. Prasanna
Uday S. Shukla
Sartaj Sahni

9 :0 0 a m - 1 0 :0 0 a m
KEYNOTE ADDRESS
"Collaboratory for Info-Bio-Nano Simulations"
Priya Vashishta
University of Southern California

Priya Vashishta is the Director of High Performance Computing Center at the University of Southern California. He is a professor in the Departments of Materials Science & Engineering and Computer Science, and Physics and Biomedical Engineering. Prior to joining USC, during 1990-2002, he was Cray Research Professor of Computational Sciences and the founding director of the Concurrent Computing Laboratory for Materials Simulations at the Louisiana State University. From 1972-1990, he was at the Argonne National Laboratory as a Senior Scientist and the Director of the Solid State Sciences Division. His research includes developing multiscale simulation approach that combines electronic structure, molecular dynamics, and finiteelement methods. Visualization tools are also being designed to analyze simulations in immersive and interactive virtual environments. These large-scale multimillion atom simulations have been executed with highly efficient, portable and scalable, multiresolution algorithms.
 

1 0 :3 0 a m - 1 2 :3 0 p m
SESSION I
Algorithms I
Chair: Bhabani Sinha
Indian Statistical Institute

2-D Wavelet Transform Enhancement on General- Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation
D. Chaver, C. Tenllado, L. Piñuel, M. Prieto, and F. Tirado, Universidad Complutense

A General Data Layout for Distributed Consistency in Data Parallel Applications
Roxana Diaconescu, Norwegian University of Science and Technology

A Parallel DFA Minimization Algorithm
Ambuj Tewari, Utkarsh Srivastava, and P. Gupta, Indian Institute of Technology, Kanpur

Accelerating the CKY Parsing using FPGAs
Jacir L. Bordim, Yasuaki Ito, and Koji Nakano, Japan Advanced Institute of Science and Technology

Duplication based Scheduling Algorithm for Interconnection Constrained Distributed Memory Machines
Savina Bansal, Padam Kumar, and Kuldip Singh, Indian Institute of Technology, Roorkee

Evaluating Arithmetic Expressions using Tree Contraction: A Fast and Scalable Parallel Implementation for Symmetric Multiprocessors (SMPS)
David A. Bader, Sukanya Sreshta, and Nina R. Weisse-Bernstein, University of New Mexico
 

1 0 :3 0 a m - 1 2 :3 0 p m
SESSION II
Architecture I
Chair: Michel Cosnard
INRIA, France

Dead-block Elimination in Cache: A Mechanism to Reduce I-Cache Power Consumption in High Performance Microprocessors
Mohan G. Kabadi, Natarajan Kannan, Palanidaran Chidambaram, Suriya Narayanan, M. Subramanian, and Ranjani Parthasarathi, Anna University

Exploiting Web Document Structure to Improve Storage Management in Proxy Caches
Abdolreza Abhari, Sivarama Dandamudi, and Shikharesh Majumdar, Carleton University

High Performance Multiprocessor Architecture Design Methodology for Application-Specific Embedded Systems
Syed Saif Abrar, Phillips Semiconductors, Bangalore

LLM: A Low Latency Messaging Infrastructure for Linux Clusters
R. K. Shyamasundar, Basant Rajan, Manish Prasad, and Amit Jain, Tata Institute of Fundamental Research

Low-Power High-Performance Adaptive Computing Architectures for Multimedia Processing
Rama Sangireddy and Arun K. Somani, Iowa State University
 

1 :3 0 p m - 2 :3 0 p m
KEYNOTE ADDRESS
"Beyond FPGAs, Field Programmable Systems"
Patrick Lysaght
Xilinx Research Labs

Patrick Lysaght is a Senior Director in Xilinx Research Labs where he leads research into emerging design technologies. Previously, he worked in research, development, marketing, technical support, sales and education in Scotland, for such organizations as the Institute for Systems Level Integration, the University of Strathclyde and Hewlett Packard. Patrick holds BSc and MSc degrees in electronics. He has published forty technical papers relating to dynamically reconfigurable logic. He is a chairman of the steering committee for FPL, the world’s largest field programmable logic conference.
 

2 :4 5 p m - 4 :4 5 p m
SESSION III
Systems Software I
Chair: Rajib Mall
Indian Institute of Technology, Kharagpur

CORBA-as-Needed: A Technique to Construct High Performance CORBA Applications
Hui Dai, Shivakant Mishra, University of Colorado and Matti A. Hiltunen, AT&T Research Labs

Automatic Search for Performance Problems in Parallel and Distributed Programs by using Multi-Experiment Analysis
Thomas Fahringer and Clovis Seragiotto Jr., University of Vienna

An Adaptive Value-based Scheduler and its RT-Linux Implementation
S. Swaminathan and G. Manimaran, Iowa State University

Effective Selection of Partition Sizes for Moldable Scheduling of Parallel Jobs
Srividya Srinivasan, Vijay Subramani, Rajkumar Kettimuthu, Praveen Holenarsipur, and P. Sadayappan, Ohio State University

Runtime Support for Multigrain and Multiparadigm Parallelism
Panagiotis E. Hadjidoukas, Eleftherios D. Polychronopoulos, and Theodore S. Papatheodorou, University of Patras

A Fully Compliant OpenMP Implementation on Software Distributed Shared Memory
Sung-Woo Lee, Sven Karlsson, and Mats Brorsson, Royal Institute of Technology
 

2 :4 5 p m - 4 :4 5 p m
SESSION IV
Networks
Chair: Abhay Karandikar
Indian Institute of Technology, Mumbai

A Fast Connection-Time Redirection Mechanism for Internet Application Scalability
Michael Haungs, Raju Pandey, Earl Barr, University of California, Davis, and J. Fritz Barnes, Vanderbilt University

Algorithms for Switch-Scheduling in the Multimedia Router for LANs
Indrani Paul, Sudhakar Yalamanchili, Georgia Institute of Technology, and Jose Duato, Universite Politecnia de Valencia

An Efficient Resource Sharing Scheme for Dependable Real-Time Communication in Multihop Networks
G. Ranjith and C. Siva Ram Murthy, Indian Institute of Technology, Chennai

Improving Web Server Performance by Network Aware Data Buffering and Caching
Sourav Sen and Y. Narahari, Indian Institute of Science

Wraps Scheduling and its Efficient Implementation on Network Processors
Xiaotong Zhuang and Jian Liu, Georgia Institute of Technology

Performance Comparison of Pipelined Hash Joins on Workstation Clusters
Kenji Imasaki, Hong Nguyen, and Sivarama P. Dandamudi, Carleton University
 

5 :0 0 p m - 7 :0 0 p m
POSTER/PRESENTATION SESSION
This session will emphasize novel applications of high performance computing. It will offer a brief presentation time for each poster followed by a walk-up and talk setting.

For submission details, contact:
Co-Chairs:
Paul Roe
Email: p.roe@qut.edu.au
Rajkumar Buyya
Email: rajkumar@buyya.com
 

7 :0 0 p m - 1 0 :0 0 p m
BANQUET AND CULTURAL PROGRAM
Speaker: Suresh Vaswani, Wipro Infotech